RXCHDT=Val_0x0
Receive FIFO Configuration Register 0
| RXCHDT | This bit field programs the trigger level in the RX FIFO at which the Received Data Available interrupt and DMA request is generated (Trigger Level = Programmed Value + 1). Valid values of the I2S_RFCR0[RXCHDT] bit field: 0 to RX FIFO depth - 1. If an illegal value is programmed, this bit field saturates to RX FIFO depth - 1. For more information about FIFO depth, refer to Section I2S Overview. The channel must be disabled prior to any changes in this value (that is, I2S_RER0[RXCHENX] = 0x0). 0 (Val_0x0): Interrupt trigger and DMA request asserted when FIFO level is 1 1 (Val_0x1): Interrupt trigger and DMA request asserted when FIFO level is 2 2 (Val_0x2): Interrupt trigger and DMA request asserted when FIFO level is 3 3 (Val_0x3): Interrupt trigger and DMA request asserted when FIFO level is 4 4 (Val_0x4): Interrupt trigger and DMA request asserted when FIFO level is 5 5 (Val_0x5): Interrupt trigger and DMA request asserted when FIFO level is 6 6 (Val_0x6): Interrupt trigger and DMA request asserted when FIFO level is 7 7 (Val_0x7): Interrupt trigger and DMA request asserted when FIFO level is 8 8 (Val_0x8): Interrupt trigger and DMA request asserted when FIFO level is 9 9 (Val_0x9): Interrupt trigger and DMA request asserted when FIFO level is 10 10 (Val_0xA): Interrupt trigger and DMA request asserted when FIFO level is 11 11 (Val_0xB): Interrupt trigger and DMA request asserted when FIFO level is 12 12 (Val_0xC): Interrupt trigger and DMA request asserted when FIFO level is 13 13 (Val_0xD): Interrupt trigger and DMA request asserted when FIFO level is 14 14 (Val_0xE): Interrupt trigger and DMA request asserted when FIFO level is 15 15 (Val_0xF): Interrupt trigger and DMA request asserted when FIFO level is 16 |